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WM0834, WM0838
Production Data Sept 1996 Rev 2.0
8-Bit ADCs with Serial Interface and Configurable Input Multiplexer
Description
WM0834 and WM0838 are 8-bit analogue to digital converters (ADC) with configurable 4-input and 8-input multiplexers respectively and a serial I/O interface. Assignment of the multiplexer inputs is configured before each conversion via the serial data input to give single-ended or differential operation for the selected inputs. A mixture of input configurations can be used in the same application. WM0838 also has a pseudo-differential configuration where all 8 inputs can be refered to a common input at an arbitrary voltage. Serial communcation with WM0834/8 is via Data In (DI) and Data Out (DO) wires under the control of clock and chip select inputs. A high output at the SARS pin indicates when the conversion is in progress. To initiate a conversion chip enable is held low and data is input to DI on the rising edge of the clock, comprising, a start bit, and bits to set up the input configuration and polarity. After a half clock cycle delay conversion results appear at DO on the falling edge of the clock, MSB first, concurrently with A-D conversion. This is followed by the results LSB first, indicated by the falling edge of SARS. WM0838 has a shift enable (SE) input used to control the LSB first output on DO. WM0834/8 operate on 5V and 3.3V supply voltages and are available in small outline and DIP packages for commercial (0 to 70OC) and industrial (-40 to 85OC) temperature ranges.
Features
* Functionally Equivalent to National Semiconductor ADC0834 and ADC0838 without the Internal Zener Regulator Network 4-input (WM0834) or 8-input (WM0838) MUX options Reference input operates ratiometrically or with a fixed reference Input range 0 to Vcc with Vcc Reference 5V and 3.3V variants Total Unadjusted Error: 1 LSB 8-bit resolution Low Power 32 s conversion time at fclock = 250 kHz Serial I/O interface WM0834 packages: 14 pin SO & DIP WM0838 packages: 20 pin wide-body SO & DIP
* * * * * * * * * *
Applications
* * * * Embedding with remote sensors Equipment health monitoring Automotive Industrial control
Block Diagram
CS CLK DI VREF CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM AGND
1
Internal CS
Input Latch
Mux Select Start Conv
Vcc
Comparator
WM0834 4 Inputs
Input MUX
DAC & SAR Logic
Control Logic
SE
2
SARS
WM0838 8 Inputs
Output Shift Register
DO DGND
WM0834/8
Notes: 1. Internally tied to AGND for WM0834 2. Not available on WM0834
Production Data data sheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics standard terms and conditions.
Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK
(c) 1996 Wolfson Microelectronics
Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 email: admin@wolfson.co.uk www: http://www.wolfson.co.uk
WM0834, WM0838
Pin Configuration
Top View WM0834 : N(DIP) and D (SO) packages WM0838: N(DIP) and DW (SO) packages
Ordering Information
5V devices DEVICE WM0834CN WM0834CD WM0834IN WM0834ID WM0838CN WM0838CDW WM0838IN WM0838IDW 3.3V devices DEVICE WM0834LCN WM0834LCD WM0834LIN WM0834LID WM0838LCN WM0838LCDW WM0838LIN WM0838LIDW TEMP. RANGE 0o C to 70oC 0o C to 70oC -40 oC to 85o C -40 oC to 85o C 0o C to 70oC 0o C to 70oC -40 oC to 85o C -40 oC to 85o C PACKAGE 14 pin plastic DIP 14 pin plastic SO 14 pin plastic DIP 14 pin plastic SO 20 pin plastic DIP 20 pin plastic SO 20 pin plastic DIP 20 pin plastic SO
WM0834 WM0838
TEMP. RANGE 0o C to 70oC 0o C to 70oC -40 oC to 85oC -40 oC to 85oC 0o C to 70oC 0o C to 70oC -40 oC to 85oC -40 oC to 85oC
PACKAGE 14 pin plastic DIP 14 pin plastic SO 14 pin plastic DIP 14 pin plastic SO 20 pin plastic DIP 20 pin plastic SO 20 pin plastic DIP 20 pin plastic SO
Absolute Maximum Ratings (note 1) Supply Voltage, Vcc (note 2) . . . . . . . . . . . 6.5 V Input voltage range: Digital Inputs . . . . GND - 0.3 V, VCC + 0.3 V Analogue inputs . . . GND - 0.3 V, VCC + 0.3 V Input current, any pin (note 3) . . . . . . 5 mA Total Input current for package . . . . . . 20 mA
Operating temperature range, TA . . . . TMIN to TMAX WM083_C_ (C suffix) . . . . . . . . . 0 oC to +70o C WM083_I_ (I suffix) . . . . . . . . . . -40oC to +85o C Storage Temperature . . . . . . . . - 65oC to +150o C Soldering Information: Lead Temperature 1.6 mm (1/16) from case for 10 seconds: D, DW or N package . . . . . . . 260o C
Recommended Operating Conditions (5V)
Supply voltage High level input voltage Low level input voltage Clock frequency Clock duty cycle (see Note 4) Pulse duration CS high Operating free-air temperature SYMBOL VCC VIH VIL fclock Dclk twH(CS) TA TA MIN 4.5 2 10 40 220 0 -40 70 85 NOMINAL 5 MAX 5.5 0.8 600 60 UNIT V V V KHz % ns o C
C suffix I Suffix
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WM0834, WM0838
Electrical Characteristics (5V)
VCC = 5.0V, VREF = 5V, fCLK = 250 KHz, TA = TMIN to TMAX , tr = tf = 20ns, unless otherwise stated. PARAMETER Digital Inputs High level output voltage Low level output voltage High level input current Low level input current High level output (source) current Low level output (sink) current High impedance-state output current (DO) Input capacitance Output capacitance Converter and Multiplexer Total unadjusted error Differential Linearity Supply voltage variation error Common mode error Common mode input voltage range Standby input leakage current (note 10) SYMBOL VOH VOL IIH IIL IOH IOL IOZ Ci Co VREF = 5 V. (note 7) (note 8) Vs(error) VCC = 4.75 V to 5.25 V Differential mode VICR (note 9) II(stdby) On-channel VI = 5 V at ON ch. Off-channel VI = 0 V at OFF ch. On-channel VI = 0 V at ON ch. Off-channel VI = 5 V at OFF ch. Excluding MUX addressing time TUE TEST CONDITIONS VCC = 4.75 V, IOH = -360 mA VCC = 4.75 V, IOH = -10 mA VCC = 5.25 V, IOH = 1.6 mA VIH = 5 V VIL = 0 V VOH = 0 V VOL = VCC VO = 5 V VO = 0 V MIN 2.4 4.5 0.005 -0.005 -24 26 0.01 -0.01 5 5 0.4 1 -1 TYP MAX UNIT V V V A A mA mA A A pF pF LSB Bits LSB LSB V A A A A clock periods k
-6.5 8
3 -3
1 8 1/16 1/16 GND-0.05 VCC+0.05 1 -1 -1 1 8 1/4 1/4
Conversion time Reference Inputs Input resistance to reference ladder Total device Supply current Timing Parameters Setup time, CS low or data valid before clock Hold time, data valid after clock Propagation delay time, output data after clock Output disable time, DO after CS
tconv
Ri(REF)
1.3
2.4
5.9
ICC tsu th MSB data first. CL = 100 pF LSB data first. CL = 100 pF CL = 10 pF, RL = 10 k CL = 100 pF, RL = 2 k 350 90
0.6
1.25
mA ns ns
tpd tdis
125
1500 600 250 500
ns ns ns ns
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WM0834, WM0838
Recommended Operating Conditions (3.3V)
Supply voltage High level input voltage Low level input voltage Clock frequency (Vcc = 3.3V) Clock duty cycle (see Note 4) Pulse duration CS high Operating free-air temperature SYMBOL VCC VIH VIL fclock Dclk twH(CS) TA TA MIN 2.7 2 10 40 220 0 -40 NOMINAL 3.3 MAX 3.6 0.8 600 60 70 85 UNIT V V V KHz % ns o C
C suffix I Suffix
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WM0834, WM0838
Electrical Characteristics (3.3V)
VCC = 3.3V, fCLK = 250 KHz, TA = TMIN to TMAX , tr = tf = 20ns, unless otherwise stated. PARAMETER Digital Inputs High level output voltage Low level output voltage High level input current Low level input current High level output (source) current Low level output (sink) current High impedance-state output current (DO) Input capacitance Output capacitance Converter and Multiplexer Total unadjusted error Differential Linearity Supply voltage variation error Common mode error Common mode input voltage range Standby input leakage current (note 10) SYMBOL VOH VOL IIH IIL IOH IOL IOZ Ci Co VREF = 3.3 V. (note 7) (note 8) Vs(error) VCC = 3.0 V to 3.6 V Differential mode VICR (note 9) II(stdby) On-channel VI =3.3 V at ON ch. Off-channel VI = 0 V at OFF ch. On-channel VI = 0 V at ON ch. Off-channel VI =3.3V at OFF ch Excluding MUX addressing time TUE TEST CONDITIONS VCC = 3.0 V, IOH = -360 mA VCC = 3.0V, IOH = -10 mA VCC =3.0V, IOH = 1.6 mA VIH = 3.6V VIL = 0 V VOH = 0 V, TA = 25o C VOL = VCC, TA = 25o C VO = 3.3 V, TA = 25o C VO = 0 V, TA = 25o C MIN 2.4 2.8 0.005 -0.005 15 16 0.01 -0.01 5 5 0.4 1 -1 TYP MAX UNIT V V V A A mA mA A A pF pF LSB Bits LSB LSB V A A A A clock periods k
6.5 8
3 -3
1 8 1/16 1/16 GND-0.05 VCC+0.05 1 -1 -1 1 8 1/4 1/4
Conversion time Reference Inputs Input resistance to reference ladder Total device Supply current Timing Parameters Setup time, CS low or data valid before clock Hold time, data valid after clock Propagation delay time, output data after clock Output disable time, DO after CS
tconv
Ri(REF)
1.3
2.4
5.9
ICC tsu th MSB data first. CL = 100 pF LSB data first. CL = 100 pF CL = 10 pF, RL = 10 k CL = 100 pF, RL = 2 k 350 90
0.2
0.75
mA ns ns
tpd tdis
500 200 80 250
ns ns ns ns
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WM0834, WM0838
Electrical Characteristics (continued)
Notes: 1. Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating range limits are given under Recommended Operating Conditions. Guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. 2. All voltage values, except differential voltages are with respect to the ground. When the input voltage VIN at any pin exceeds the power supply rails (GND > VIN > VCC) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA supply current to four. A clock duty cycle range of 40% to 60% ensures correct operation at all clock frequencies. For a clock with a duty cycle outside these limits, the minimum time the clock is high or low must be at least 666 ns, with the maximum time for clock high or low being 60 ms. All typical values are at VCC = 5 V, TA = 25 oC for 5V devices and VCC = 3.3 V, T A = 25o C for 3.3V devices. 6. All parameters are measured under open-loop conditions with zero common mode input voltage (unless otherwise stated). 7. Total Unadjusted Error (TUE) is the sum of integral linearity error, zero code error and full scale error over the output code range. 8. A Differential linearity of "n" bits ensures a code width exist to "n" bits. Hence a Differential Linearity of 8 bits for an 8 bit ADC guarantees no missing codes. 9. For VIN (-) greater than or equal to VIN(+) the digital output code will be 00 Hex. Connected to each analogue input are two diodes which will forward conduct for a diode drop outside the supply rails, VCC and GND. If an analogue input voltage does not exceed the supply voltage by more than 50 mV, the output code will be correct. To use an absolute input voltage range of 0 to VCC a minimum VCC - 0.05 V is required for all variations of temperature. Care should be exercised when testing at low VCC levels with a maximum analogue voltage as this can cause the input diode to conduct, especially at high temperature, and cause errors for analogue inputs near full scale. 10. Standby input leakage currents, are currents going in or out of the on or off channels when the ADC is not performing conversion and the clock input is in a high or low steady-state condition.
3.
4.
5.
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WM0834, WM0838
Test Circuits and Waveforms
Output Disable Time Voltage Waveforms and Test Circuits
Standby Leakage Current Test Circuit
Detailed Timing Diagrams
Data Input Timing Data Output Timing
Vcc
Vcc
CLK
50%
50%
CLK tsu
GND Vcc
50%
50%
tsu CS
0.4V
t DO
(Data Out)
pd
t
GND
pd
Vcc 50% 50%
th DI
2V 2V 0.4V
(Data In)
th
0.4V
GND Vcc
tsu SE
50%
GND Vcc
GND
GND
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WM0834, WM0838
Functional Timing Diagrams
WM0834 Timing
WM0838 Timing
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WM0834, WM0838
Pin Descriptions
WM0834 Pin Name 1 NC 2 CS 3 4 5 6 7 8 9 10 11 CH0 CH1 CH2 CH3 DGND AGND VREF DO SARS WM0832 Pin Name Type 1 CH0 Analogue input 2 3 4 5 6 7 8 9 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input
Type Digital Analogue input Analogue input Analogue input Analogue input Supply Supply Analogue input Digital output Digital output
12 13 14
CLK DI VCC
Digital input Digital input Supply
Function No connection Chip Select (active low) Channel 0 input to multiplexer (MUX) Channel 1 input to multiplexer (MUX) Channel 2 input to multiplexer (MUX) Channel 3 input to multiplexer (MUX) Digital ground pin Analogue ground pin Voltage reference input Data output Successive approximation registar status line Clock input Data input Positive supply voltage
10 11 12 13 14 15
DGND AGND VREF SE DO SARS
Supply Supply Analogue input Digital input Digital output Digital output
16 17 18 19 20
CLK DI CS NC VCC
Digital input Digital input Digital
Supply
Function Channel 0 input to multiplexer (MUX) Channel 1 input to multiplexer (MUX) Channel 2 input to multiplexer (MUX) Channel 3 input to multiplexer (MUX) Channel 4 input to multiplexer (MUX) Channel 5 input to multiplexer (MUX) Channel 6 input to multiplexer (MUX) Channel 7 input to multiplexer (MUX) Common input for pseudo differential mode Digital ground pin Analogue ground pin Voltage reference input Shift enable control line (active low) Data Output Successive approximation register status line output Clock input Data input Chip Select (active low) No connection Positive supply voltage
Device No WM0834 WM0838
Multiplexer / Package Options Number of Analogue Channels Single Ended Differential 4 2 8 4
Number of Package Pins 14 20
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WM0834, WM0838
Functional Description
Multiplexer Operation and Addressing WM0834 and WM0838 use an input multiplexer scheme thet provides multiple analogue channels, configurable for single-ended or differential operation and also for WM0838, a pseudo-differential mode that will perform an analogue to digital (A/D) conversion of the voltage difference between any analogue input and a common terminal (COM). WM0834/8 uses a successive approximation routine to perform A/D conversion that employs a sample data comparator structure which always performs conversion on a differential voltage. Conversion takes place on the voltage difference between assigned "+" and "-" inputs and the converter expects the "+" input to be the most positive. If the "+" input is more negative than "-" then the converter gives an all zeros output. Assignment of inputs is made for a single-ended signal between an "+" input and analogue ground (AGND) or COM for WM0838, or for differential inputs between adjacent pairs of inputs of either polarity. The COM input of WM0838 acts as the "-" input for pseudodifferential "+" inputs and can be an arbitrary voltage such as an analogue common not at ground potential in single supply applications. Prior to the start of every conversion the input configuration is assigned during the MUX addressing sequence achieved by serially shifting data into the Data Input (DI) on the rising edges of the clock input. The MUX address selects which analogue inputs are enabled, either single-ended, differential or pseudodifferential (WM0838). For differential inputs the polarity of the selected pairs of adjacent inputs are also assigned. Differential inputs can only be assigned to adjacent channel pairs. The MUX addressing tables give full details of input assignments. Initiating Conversion and the Digital Interface WM0834 and WM0838 are controlled from a processor via a serial interface comprising Data In (DI) and Data Out (DO), Chip Select (CS) and Clock (CLK) inputs and a SAR Status (SARS) output. A conversion is initiated by pulling the chip select (CS) line low. CS must be kept low for an entire conversion. The start bit and the MUX assignment bits on DI are clocked in on the rising edges of the clock input, which may be generated by the processor or run continuously. WM0834 uses three MUX assignment bits and WM0838 uses four. When the logic "1" start bit is clocked into the start conversion location of the multiplexer input register, the analogue MUX inputs are selected. After 1/2 a clock period delay to allow for the selected MUX output to settle, the conversion commences using the successive approximation technique. At this time, the SARS output goes high to indicate a conversion is in progress and the DI input is disabled. When conversion begins, the A/D conversion result from the output of the SARS comparator appears at the DO output on each falling edge of the clock (see Functional Timing Diagrams). With the successive approximation A/D conversion routine, the analogue input is compared with the output of a digital to analogue converter (DAC) for each bit by the SARS comparator and a decision made on whether the analogue input is higher or lower than the DAC output. Successive bits, MSB to LSB are input to the DAC and remain in its input if the analogue comparison decides the analogue input is higher than the DAC output. If not, the bit is removed from the DAC input. The output from the SARS comparator forms the resulting input to the DAC and the A/D conversion output, and is read by the processor as conversion takes place in MSB to LSB order. After 8 clock periods, the conversion is complete and this is indicated by SARS being brought low a 1/2 clock period later. All bits of the conversion are stored in an output shift register after a conversion has completed and MSB first data has been output. For WM0838, the commencement of output data in a LSB first format can be controlled by use of the SE input. If the SE input is held high, the LSB output will remain on the DO output. When SE is brought low, LSB first data output will begin on DO. After 8-bits of LSB first data have been output, the DO output goes low and remains low until CS is brought high, when outputs (DO & SARS) go into a high impedance state.
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WM0834, WM0838
Functional Description (continued)
WM0834 MUX Addressing MUX Address Channel Number SGL/DIF ODD/EVEN Select bit 0 1 Differential MUX Mode (Between adjacent pairs of points) 0 0 0 + 0 0 1 0 1 0 + 0 1 1 Single Ended MUX Mode (between selected input(s) and AGND) 1 0 0 + 1 0 1 1 1 0 + 1 1 1
2
3
+ -
+
+ +
Note: Analogue common input 'COM' used with single ended mode is internally tied to AGND All internal registers are cleared when CS is high. To initiate another conversion, CS must make a high to low transition and MUX address assignments input to DI. The DI inpit and DO output can be tied together and controlled via a bidirectional processor I/O bit line. Reference Input The analogue input voltage range Vmax to Vmin for differential and pseudo-differential input is defined by the voltage applied to the reference input with respect to AGND. WM0834/8 can be used in ratiometric appliacations or those requiring absolute accuracy. A ratiometric input is typically the Vcc and is the same supply used to power analogue input circuitry and sensors. In such systems under a given input condition, the same code will be output with variations in supply voltage, because the same ratio change occurs in both the analogue and reference input to the A/D. When used in applications requiring absolute accuracy, a suitable time and temperature stable voltage reference source should be used. The voltage source used to drive the reference input should be capable of driving the 2.4k typical of the SAR resistor ladder. The maximum input voltage to the reference input is the Vcc supply voltage. The minimum can be as least as low as 1V to allow for direct conversion of sensor outputs with output voltage ranges less than 5V. Analogue Inputs While sampling the analogue inputs, short spikes of current enter a "+" input and flow out of the corresponding "-" input at the clock edges during conversion. This current does not cause errors as it decays rapidly and the internal comparator is strobed at the end of a clock period. Care should be exercised if bypass capacitors are used at the inputs as an apparant offset error can be caused by the capacitor averaging the input current and developing a voltage across the source resistance. Bypass capacitors should not be used with a source resistance greater than 1k. In considering error sources, input leakage current will also cause a voltage drop across the source resistance and hence, high impedance sources should be buffered. In differential mode, there is a 1/2 clock period interval between sampling the "+" and the "-" inputs. If there is a change in common mode voltage during this interval, an errorcould notionally result. For a sinusoidal common mode signal, the error is given by: VERROR = VPEAK (2fCM) (1/(2fCLK)) Where VPEAK = peak common mode voltage fCM = common mode signal frequency fCLK = clock frequency
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WM0834, WM0838
WM0838 MUX Addressing MUX Address SGL/ ODD/ Select biits Channel Number DIF EVEN 1 0 0 1 2 3 4 5 Differential MUX Mode (between adjacent pairs of inputs) 0 0 0 0 + 0 0 0 1 + 0 0 1 0 + 0 0 1 1 0 1 0 0 + 0 1 0 1 + 0 1 1 0 + 0 1 1 1 Single Ended MUX Mode (between selected input(s) and 'COM' pseudo analogue ground) 1 0 0 0 + 1 0 0 1 + 1 0 1 0 + 1 0 1 1 1 1 0 0 + 1 1 0 1 + 1 1 1 0 + 1 1 1 1
6
7
COM
+
-
-
+ -
+
+
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WM0834, WM0838
Performance Data
WM0834: Total Unadjusted Error
1 0.75 0.5
Error (lsbs)
0.25 0 -0.25 -0.5 -0.75 -1 0 32 64 96 128 160 192 224 256
Code WM0838: Total Unadjusted Error
1 0.75 0.5
Error (lsbs)
0.25 0 -0.25 -0.5 -0.75 -1 0 32 64 96 128 160 192 224 256
Code
Test conditions: VDD = 5V, VREF = 5V, Temp = 25o C, FCLK = 250kHz
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WM0834, WM0838
Package Descriptions
Plastic Small-Outline Package D - 8 pins shown
4.00 3.80 8
A 5
6.20 5.80
1 1.75 1.35
4 0.50 0.25 0.19 x 45O NOM 0.25
0.51 0.25 0.10 0.33 Pin spacing 1.27 B.S.C. 0O to 8O 1.27 0.40
Dimension 'A' Variations N 8 14 16 Min 4.80 8.55 9.80 Max 5.00 8.75 10.00
Notes: A. Dimensions in millimeters. B. Complies with Jedec standard MS-012. C. This drawing is subject to change without notice. D. Body dimensions do not include mold flash or protrusion. E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall not exceed 0.25mm.
Rev. 1 November 96
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WM0834, WM0838
Package Description
Wide body Plastic Small-Outline Package DW - 16 pin shown
1,27 B.S.C. 0,51 0,33 16 0,25 M 9 DIM A MAX 10,50 13,00 15,60 18,10 PINS**
16
20
24
28
10,65 10,00 7,60 7,40
A MIN
10,10
12,60
15,20
17,70
0.75 x 45 0 0.25 x 45 0
1 A
8 Gauge Plane
0o - 8o 1,27 0,40
2,65 2,35
0,30 0,10
0,10
0,33 0,23
Notes: A. Dimensions in millimeters. B. Complies with Jedec standard MS-013. C. This drawing is subject to change without notice. D. Body dimensions do not include mold flash or protrusion. E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall not exceed 0.25mm.
Rev. 1 November 96
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WM0834, WM0838
Package Descriptions
Dual-In-Line Package
N or P
N
0.325 0.290 0.015 Min.
1
N/2
A 0.070 Max.
0.280 0.240
0.210 Max. 105O 90O 0.014 0.008 0.150 0.115 0.005 Min. Pin spacing 0.100 B.S.C. 0.045 0.030 0.022 0.014 Seating plane
Dimension 'A' Variations N 8 14 16 20 Min 0.355 0.735 0.735 0.940 Max 0.400 0.775 0.775 0.975
Notes: A. Dimensions are in inches B. Falls within JEDEC MS-001( 20 pin package is shorter than MS-001) C. N is the maximum number of terminals D. All end pins are partial width pins as shown, except the 14 pin package which is full width.
Rev. 1 November 96
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Wolfson Microelectronics

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